s6j31 10 s eries 32 - bit microcontroller traveo family fact sheet cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408- 943 - 2600 document number: 002- 08974 rev. *a revised april 19, 2016 the traveo ? family s6j3110 , feature s 32 - bit risc microcontrollers with an arm ? cortex ? - r5 core and operate at 144 mhz. 4 mb of flash memory can cor respond also to the soft ware capacity which will increase in the future . first body application mcu with c an -fd as a communication interface. can - fd is compatible with the conventional can and it can shorten the time of reprograming by high - speed communication. moreover,this miocrocontroller has she(secure hardware extension) as security function. it will prevent the extractraction and alteration of the data or keys. this microcontroller can control safely and quickly the circumference function of body in which an increase will be expected from now on. features ? 32bit arm ? cortex ? - r5 cpu core ? clock ? maximum clock freque ncy : 144 mhz , 96mhz* ? dma controller : 16 channels ? external interrupt : 16 channels ? base timer : 30 channels ? 32- bit free- run timer : 6 channels ? 32- bit input capture: 12 channels ? 32- bit output compare : 12 channels ? 12- bit a/d converter : 64, 56* channels ( 2 units t otal ) ? real time clock ? multi - function serial interface : 22, 4* channels , selectable from uart/csio/lin /i2c ? can - fd (192 msb [reception] ): 2, 1* channels ? exclusion access memory ? watchdog timer : 1 channel (sw)+1 channel (hw) ? crc generation : 1 channel ? secure hardwar e extension ? general purpose i/o port : 1 50, 116* ? built - in cr oscillator ? debug interface ? jtag debug port ? partial - wakeup function ? low voltage detector ? clock supervisor ? power supply : 1 power voltage(5v) * spec for s6j311a h xb , s6j311 9h xb , s6j311 8h xb pac kage ex ample o f reference plastic ? teqfp 176,176pin product lineup part number parameter s6j311ex xb s6j311dx xb s6j311cx xb s6j311bx xb main flash(byte) 4096k+64k 3072k+64k 2048k+64k 1536k+64k work flash(byte) 112k 112k 112k 112k ram(byte) 320k 256k 192k 128k backup ram(byte) 64k 64k 64k 64k part number parameter s6j311ah xb s6j3119h xb s6j3118h x b main flash(byte) 1024k+64k 768k+64k 512k+64k work flash(byte) 48k 48k 48k ram(byte) 80k 64k 48k backup ram(byte) 8k 8k 8k ordering information part number package s6j311eja b sex0000 plastic teqfp (0.5mm pitch ), 176pin s6j311dja b sex0000 s6j311cja b sex0000 s6j311bja b sex0000 s6j311eha b sex0000 plastic teqfp (0.5mm pitch ), 144pin s6j311dha b sex0000 s6j311cha b sex0000 s6j311bha b sex0000 s6j311 a ha b sex0000 plastic teqfp (0.5mm pitch ), 144pin s6j311 9 ha b sex0000 s6j311 8 ha b sex0000 s6j311ej bb sex0000 plastic teqfp (0.5mm pitch ), 176pin s6j311dj bb sex0000 s6j311cj bb sex0000 s6j311bj bb sex0000 s6j311eh bb sex0000 plastic teqfp (0.5mm pitch ), 144pin s6j311dh bb sex0000 s6j311ch bb se x0000 s6j311bh bb sex0000 s6j311 a h bb sex0000 plastic teqfp (0.5mm pitch ), 144pin s6j311 9 h bb sex0000 s6j311 8 h bb sex0000
document number: 002- 08974 rev. *a page 2 of 4 s6j312 0 s eries b lock diagram block diagram of s6j311ex xb , s6j311dx xb ,s6j311cx xb ,s6j311bx xb c p p common peri #0 group common peri #1 group common peri #2 group common peri #0 group sys te m controller(sysc) sysc1 memory & config group core group ( 1 - core) debug group (coresighttm) dap tc r am #0 (2bank) 64kb (32kb 2) bootrom 16kb timing protection (tpu) #0 debug i/f (jtag/swd) ahb - m apb - s apb - m procceser b0tcm atcm #0 b1tcm #0 llpp ax i32 - m ahb32 axi - m axi - s c pu #0 irc #0 512 vectors r am security ahb - 64 apb - 32 jtag wakeup i$ #0 16kb d$ #0 16kb mpu #0 dmac complex #0 - dmac 16.ch - reloadtimer 4ch jtag_sw clktck clk_dbg trace group system sram 16kb wakeup request #0 etm tm # 0 debug apb debug apb atb ahb 2apb (priviledge protection) trace i/ f(8pin) etb (trace buffer) 16kb a h b - 64 security checker cortex tm - r5f clk_ atb flash group i/f low latency peripheral bus matrix (llpbm) bus config group - bus performance counters - misc register module from/to commonperi#2 a h b - 32 from/to commonperi#2 dma c config a xi - 64 a h b - 32 axi - 64 axi - 64 a h b - 32 a h b - 32 a h b - 32 from/to flash group from/to memor y config grp. clock divide and distribution power domain 2 mcu config group ecc - ed ram i/f backup ram 4kb (8+5 bit width ram x 4) backup ram 4kb (8+5 bit width ram x 4) eicu 16ch power domain 6_0 power domain 4_ 0 ahb - 32 clk_sysc0h a hb - 32 state manage (2) clk_dma ahb - 32 power domain 1 (always on) power domain 1 (always on) eam a xi - 64 clk_ sysc1 sw - watchdog csv(for pll) high performance matrix (hpm) can - fd 1ch ahb - 32 clk_hpm2 clk_llpbm2 flash group tcflash #0 1mb + 64kb + eeflash #0 48kb workflash tcf tcf tcf a hb - 64 ahb - 64 axi - 64 atcm #0 (reg & data) (reg) (data) from/to memor y config grp. axi - 64 clk_cpu clk_fclk clk_cpu clk_memc clk_hpm clk_hpm clk_memc clk_hpm clk_memc clk_hpm clk_llpbm2 clk_llpbm clk_lcp0a clk_lcp0a clk_hpm clk_hpm clk_hpm2 clk_cpu axi - 64 clk_cpu clk_cpu clk_cpu clk_memc clk_ sysc1 clk_lcp clk_can clk_ram0h clk_ram1h clk_trc clk_cpu clk_dbg clk_she clk_she bbu bbu bbu bbu clk_llpbm2 a hb - 32 clk_llpbm clk_llpbm clk_llpbm clk_llpbm ram base timer 30ch m.f.s 4ch 32bit frt 6ch 32bit icu 12ch 32bit ocu 12ch 12bit a/dc unit0 25ch 12bit a/dc unit1 31ch peripheral bus bridge peripheral bus bridge peripheral bus bridge crc 4ch gp io dmac complex #0 (config) ppu master (cnofig) bus config group (config) h/w watchdog reset manage clock manage csv ponr state manage source clock tim er l vd fas t - cr slow - cr pll0 sscg pll0 wakeup - detect rtc power manage ext - irq 16ch n mi clock calibration clk_cpu a hb - 64 a hb - 64 clk_memc she group ppu master from/to commonperi#2 clk_hpm clk_hpm clk_she clk_hpm bbu power domain 4_1 a h b - 32 axi - 32 #0 tcram (config) from/to cor e - group clk_memc power domain 3 power domain 3 from/to ppu - slaves can pres cal er clk_can clk_comh
document number: 002- 08974 rev. *a page 3 of 4 s6j31 1 0 series document history document title: s6j3110 series, 3 2 - bit microcontroller traveo family fact sheet document number: 002- 08974 revision ecn orig. of change submission date description of change ** ? nnak 11/14/ /201 4 migrated to cypress and assigned document number 002 - 08974. no change to document contents or format. *a 5159031 hiot 03/04 /2016 updated to cypress template added she - off option and updated revision
document number: 002- 08974 rev. *a page 4 of 4 s6j31 1 0 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, ma nufacturer?s representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cy press.com/ usb wireless/rf cypress.com/wireless psoc? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support arm and cortex are the trademark s of arm limited in the eu and other countries ? cy pres s semiconductor corporation 2014 - 2016. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellectual pro perty laws and treaties of the united states and oth er countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the softw are is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the us e of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non - 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